arch/mips/jazz/irq.c

104

} else if (pending & IE_IRQ1) {

arch/mips/jazz/irq.c

90

change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);

arch/mips/kernel/smp-bmips.c

48

unsigned long bmips_tp1_irqs = IE_IRQ1;

arch/mips/sgi-ip32/ip32-irq.c

412

else if (unlikely(pending & IE_IRQ1))

arch/mips/sgi-ip32/ip32-irq.c

495

#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)

arch/mips/sni/pcimt.c

303

change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);

arch/mips/sni/pcit.c

186

clear_c0_status(IE_IRQ1);

arch/mips/sni/pcit.c

191

set_c0_status(IE_IRQ1);

arch/mips/sni/pcit.c

246

change_c0_status(ST0_IM, IE_IRQ1);