IER
writel(0x00, UART1_REG(IER));
writel(0x00, UART1_REG(IER));
writel(0x00, UART1_REG(IER));
outb(0, port + IER); /* no interrupt */
static_call(serial_out)(early_serial_base, IER, 0); /* no interrupt */
writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
ret = regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], IER), ATMEL_TC_DEF_IRQS);
xe_mmio_write32(mmio, IER(irqregs), bits);
xe_mmio_write32(mmio, IER(irqregs), 0);
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
u16 IER;
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE);
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY);
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN |
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
.IER = 0x24,
.IER = 0x24,
at91_adc_writel(st, IER, BIT(channel));
xintc_write(irqc, IER, 0);
out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */
out_8(&via[IER], 0x7f); /* disable interrupts from VIA */
(void)in_8(&via[IER]);
out_8(&via[IER], SR_INT); /* disable SR interrupt from VIA */
out_8(&via1[IER], CB1_INT | IER_CLR);
out_8(&via1[IER], CB1_INT | IER_SET);
intr, in_8(&via1[IER]), pmu_state);
out_8(&via1[IER], IER_CLR | 0x7f); /* disable all intrs */
out_8(&via1[IER], IER_SET | SR_INT | CB1_INT);
out_8(&via1[IER], IER_CLR | 0x7f); /* disable all intrs */
out_8(&via1[IER], IER_SET | SR_INT | CB1_INT);
saa7146_write(dev, IER, 0);
saa7146_write(dev, IER, 0);
writel_relaxed(INT_MASK, ctrl->regs + IER);
unsigned int IER;
queue_writel(queue, IER, MACB_TX_INT_FLAGS);
queue_writel(queue, IER, bp->rx_intr_mask);
queue_writel(queue, IER, MACB_BIT(TCOMP));
queue_writel(queue, IER,
queue->IER = GEM_IER(hw_q - 1);
queue->IER = MACB_IER;
macb_writel(lp, IER, MACB_BIT(RCOMP) |
queue_writel(bp->queues, IER, GEM_BIT(WOL));
queue_writel(bp->queues, IER, MACB_BIT(WOL));
queue_writel(queue, IER,
writel(0, dev->base + IER);
readl(dev->base + IER);
writel(1, dev->base + IER);
outb(0, IER(dev->base_addr));
outb(0x0a, IER(dev->base_addr));
outb(0, IER(dev->base_addr));
outb(0, IER(dev->base_addr));
outb(2, IER(dev->base_addr));
outb(0, IER(dev->base_addr));
outb(0, IER(iobase));
outb(0, IER(dev->base_addr));
outb(ENABLE_RTXINT, IER(dev->base_addr));
outb(0, IER(dev->base_addr));
outb(0, IER(dev->base_addr));
ADM8211_CSR_WRITE(IER, 0);
ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
ADM8211_CSR_WRITE(IER, 0);
__le32 IER; /* 0x38 CSR7 */
writel(0x00, UART1_REG(IER));
at91_usart_spi_writel(aus, IER, US_IR_RXRDY);
at91_usart_spi_writel(aus, IER, US_IR_RXRDY);
at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS);
spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
spi_writel(as, IER, SPI_BIT(OVRES));
spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
if (info->IER & UART_IER_THRI) {
info->IER &= ~UART_IER_THRI;
&& !(info->IER & UART_IER_THRI)) {
info->IER |= UART_IER_THRI;
info->IER &= ~UART_IER_THRI;
info->IER &= ~UART_IER_THRI;
info->IER |= UART_IER_THRI;
info->IER &= ~UART_IER_THRI;
if(info->IER & UART_IER_MSI)
info->IER = UART_IER_MSI;
info->IER = 0;
info->IER &= ~UART_IER_MSI;
info->IER |= UART_IER_MSI;
info->IER |= UART_IER_MSI;
info->IER |= UART_IER_MSI;
info->IER |= UART_IER_THRI;
&& !(info->IER & UART_IER_THRI)) {
info->IER |= UART_IER_THRI;
int IER; /* Interrupt Enable Register */
info->IER |= UART_IER_THRI;
info->IER &= ~MOXA_MUST_RECV_ISR;
outb(info->IER, info->ioaddr + UART_IER);
info->IER |= UART_IER_THRI;
outb(info->IER, info->ioaddr + UART_IER);
info->IER |= MOXA_MUST_RECV_ISR;
outb(info->IER, info->ioaddr + UART_IER);
info->IER |= UART_IER_THRI;
outb(info->IER, info->ioaddr + UART_IER);
if (info->IER & UART_IER_THRI)
u8 IER; /* Interrupt Enable Register */
outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
info->IER |= UART_IER_THRI;
outb(info->IER, info->ioaddr + UART_IER);
info->IER &= ~UART_IER_THRI;
outb(info->IER, info->ioaddr + UART_IER);
info->IER &= ~UART_IER_MSI;
info->IER |= UART_IER_MSI;
info->IER |= UART_IER_MSI;
outb(info->IER, info->ioaddr + UART_IER);
info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
info->IER |= MOXA_MUST_IER_EGDAI;
outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
info->IER &= ~UART_IER_RLSI;
info->IER &= ~MOXA_MUST_RECV_ISR;
outb(info->IER, info->ioaddr + UART_IER);
info->IER = 0;
i810_writew(IER, mmio, par->hw_state.ier);
par->hw_state.ier = i810_readw(IER, mmio);
saa7146_write(x, IER, saa7146_read(x, IER) & ~y);
saa7146_write(x, IER, saa7146_read(x, IER) | y);
ac97c_writel(chip, IER, word);
ac97c_writel(chip, IER, word);
ac97c_writel(chip, IER, ac97c_readl(chip, IMR) | AC97C_SR_COEVT);
atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
atiixp_write(chip, IER, CODEC_CHECK_BITS);
atiixp_write(chip, IER, 0); /* disable irqs */
atiixp_write(chip, IER,
atiixp_write(chip, IER, 0);
atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
atiixp_write(chip, IER, CODEC_CHECK_BITS);
atiixp_write(chip, IER, 0); /* disable irqs */
atiixp_write(chip, IER,
atiixp_write(chip, IER, 0);
atiixp_update(chip, IER, ATI_REG_IER_MODEM_SET_BUS_BUSY, bus_busy);
WRITEREG(A1_out | A2_out | A1_in | IIC_S | IIC_E, IER);
WRITEREG(0, IER);
WRITEREG(0, IER);
ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
i2s_write_reg(dev->i2s_base, IER, reg);
i2s_write_reg(dev->i2s_base, IER, 0);
writel(1, kmb_i2s->i2s_base + IER);
writel(0, kmb_i2s->i2s_base + IER);
writel(0, kmb_i2s->i2s_base + IER);
ssc_writel(chip->ssc->regs, IER, SSC_BIT(IER_ENDTX));