drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h

13

#define ICP_QAT_UCLO_MAX_UIMAGE (ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX)

drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h

162

struct icp_qat_uclo_page *cur_page[ICP_QAT_UCLO_MAX_CTX];

drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h

165

unsigned int new_uaddr[ICP_QAT_UCLO_MAX_CTX];

drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h

171

struct icp_qat_uclo_aeslice ae_slices[ICP_QAT_UCLO_MAX_CTX];

drivers/crypto/intel/qat/qat_common/qat_hal.c

1503

} while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX));

drivers/crypto/intel/qat/qat_common/qat_hal.c

1538

} while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX));

drivers/crypto/intel/qat/qat_common/qat_hal.c

1573

} while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX));

drivers/crypto/intel/qat/qat_common/qat_hal.c

1593

for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) {

drivers/crypto/intel/qat/qat_common/qat_hal.c

322

for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) {

drivers/crypto/intel/qat/qat_common/qat_hal.c

353

for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) {

drivers/crypto/intel/qat/qat_common/qat_hal.c

369

for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) {

drivers/crypto/intel/qat/qat_common/qat_uclo.c

1010

ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX);

drivers/crypto/intel/qat/qat_common/qat_uclo.c

2183

if (ICP_QAT_CTX_MODE(image->ae_mode) == ICP_QAT_UCLO_MAX_CTX)

drivers/crypto/intel/qat/qat_common/qat_uclo.c

2211

for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++)

drivers/crypto/intel/qat/qat_common/qat_uclo.c

812

ICP_QAT_UCLO_MAX_CTX)

drivers/crypto/intel/qat/qat_common/qat_uclo.c

955

ICP_QAT_UCLO_MAX_CTX); s++) {