arch/x86/kernel/apic/apic.c

1106

v = apic_read(APIC_LVTT);

arch/x86/kernel/apic/apic.c

1107

apic_write(APIC_LVTT, v | APIC_LVT_MASKED);

arch/x86/kernel/apic/apic.c

1135

apic_write(APIC_LVTT, APIC_LVT_MASKED);

arch/x86/kernel/apic/apic.c

1658

value = apic_read(APIC_LVTT);

arch/x86/kernel/apic/apic.c

1660

apic_write(APIC_LVTT, value);

arch/x86/kernel/apic/apic.c

2410

apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);

arch/x86/kernel/apic/apic.c

2504

apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);

arch/x86/kernel/apic/apic.c

300

apic_write(APIC_LVTT, lvtt_value);

arch/x86/kernel/apic/apic.c

442

v = apic_read(APIC_LVTT);

arch/x86/kernel/apic/apic.c

444

apic_write(APIC_LVTT, v);

arch/x86/kernel/apic/vector.c

1265

v = apic_read(APIC_LVTT);

arch/x86/kernel/apic/x2apic_savic.c

205

case APIC_LVTT:

arch/x86/kernel/apic/x2apic_savic.c

66

case APIC_LVTT:

arch/x86/kvm/lapic.c

1750

APIC_REG_MASK(APIC_LVTT) |

arch/x86/kvm/lapic.c

1901

u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &

arch/x86/kvm/lapic.c

1935

reg = kvm_lapic_get_reg(apic, APIC_LVTT);

arch/x86/kvm/lapic.c

2035

kvm_apic_local_deliver(apic, APIC_LVTT);

arch/x86/kvm/lapic.c

2420

if (reg < APIC_LVTT || reg > APIC_LVTERR)

arch/x86/kvm/lapic.c

2423

(reg - APIC_LVTT) >> 4, KVM_APIC_MAX_NR_LVT_ENTRIES);

arch/x86/kvm/lapic.c

2517

case APIC_LVTT:

arch/x86/kvm/lapic.c

2521

kvm_lapic_set_reg(apic, APIC_LVTT, val);

arch/x86/kvm/lapic.c

3048

if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))

arch/x86/kvm/lapic.h

47

#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))

arch/x86/kvm/svm/avic.c

796

case APIC_LVTT:

arch/x86/kvm/vmx/tdx.c

1085

if (pi_test_pir(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTT) &

arch/x86/kvm/vmx/tdx.c

2198

case X2APIC_MSR(APIC_LVTT):

tools/testing/selftests/kvm/x86/apic_bus_clock_test.c

72

apic_write_reg(APIC_LVTT, APIC_LVT_TIMER_ONESHOT | APIC_LVT_MASKED);