IDX
return EXP_TID_SET(IDX, pair >> 1) |
EXP_TID_SET(IDX, rcventry >> 1) |
KDETH_SET(resp->kdeth0, TID, EXP_TID_GET(tidentry, IDX));
KDETH_SET(wd->kdeth0, TID, EXP_TID_GET(tidentry, IDX));
return EXP_TID_GET(ent, IDX);
u32 tididx = EXP_TID_GET(tidinfo, IDX) << 1, rcventry;
EXP_TID_GET(tidval, IDX));
(EXP_TID_GET(tidval, IDX) & 0x3ff));
tididx = EXP_TID_GET(tidval, IDX),
#define CIX_REG_F_INT(IDX) (CIX_ERR_COMP_CLR + 0x4*(IDX+1)) /* 0x8c~0xa8 */
#define CIX_FAST_CH_INT(IDX) BIT((IDX)+9)
prod_idx |= HINIC_API_CMD_PI_SET(chain->prod_idx, IDX);
prod_idx = HINIC_API_CMD_PI_CLEAR(prod_idx, IDX);
val = HINIC_EQ_CI_CLEAR(val, IDX) &
val |= HINIC_EQ_CI_SET(eq->cons_idx, IDX) |
val = HINIC_PPF_ELECTION_CLEAR(val, IDX);
ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX);
attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX);
sq_ctxt->ci_wrapped = HINIC_SQ_CTXT_CI_SET(ci_start, IDX) |
rq_ctxt->pi_intr_attr = HINIC_RQ_CTXT_PI_SET(pi_start, IDX) |
val |= HINIC3_DMA_ATTR_INDIR_IDX_SET(HINIC3_PCIE_MSIX_ATTR_ENTRY, IDX);
val |= HINIC3_PPF_ELECTION_SET(attr->func_global_idx, IDX);
attr->ppf_idx = HINIC3_PPF_ELECTION_GET(val, IDX);
#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, IDX)])
#define EMAC_RRD(RXQ, SIZE, IDX) ((RXQ)->rrd.v_addr + (SIZE * (IDX)))
#define EMAC_RFD(RXQ, SIZE, IDX) ((RXQ)->rfd.v_addr + (SIZE * (IDX)))
#define EMAC_TPD(TXQ, SIZE, IDX) ((TXQ)->tpd.v_addr + (SIZE * (IDX)))
#define GET_RFD_BUFFER(RXQ, IDX) (&((RXQ)->rfd.rfbuff[(IDX)]))
#define GET_TPD_BUFFER(RTQ, IDX) (&((RTQ)->tpd.tpbuff[(IDX)]))
#define ENET_VLAN_TBL(IDX) (FZC_FFLP + 0x00000UL + (IDX) * 8UL)
#define L2_CLS(IDX) (FZC_FFLP + 0x20000UL + (IDX) * 8UL)
#define L3_CLS(IDX) (FZC_FFLP + 0x20010UL + (IDX) * 8UL)
#define TCAM_KEY(IDX) (FZC_FFLP + 0x20030UL + (IDX) * 8UL)
#define FLOW_KEY(IDX) (FZC_FFLP + 0x40000UL + (IDX) * 8UL)
#define FLW_PRT_SEL(IDX) (FZC_FFLP + 0x40070UL + (IDX) * 8UL)
#define HASH_TBL_ADDR(IDX) (FFLP + 0x00000UL + (IDX) * 8192UL)
#define HASH_TBL_DATA(IDX) (FFLP + 0x00008UL + (IDX) * 8192UL)
#define HASH_TBL_DATA_LOG(IDX) (FFLP + 0x00010UL + (IDX) * 8192UL)
#define DEF_RDC(IDX) (FZC_DMC + 0x00008UL + (IDX) * 0x8UL)
#define PT_DRR_WT(IDX) (FZC_DMC + 0x00028UL + (IDX) * 0x8UL)
#define PT_USE(IDX) (FZC_DMC + 0x00048UL + (IDX) * 0x8UL)
#define RX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x20000UL + (IDX) * 0x40UL)
#define RX_LOG_MASK1(IDX) (FZC_DMC + 0x20008UL + (IDX) * 0x40UL)
#define RX_LOG_VAL1(IDX) (FZC_DMC + 0x20010UL + (IDX) * 0x40UL)
#define RX_LOG_MASK2(IDX) (FZC_DMC + 0x20018UL + (IDX) * 0x40UL)
#define RX_LOG_VAL2(IDX) (FZC_DMC + 0x20020UL + (IDX) * 0x40UL)
#define RX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x20028UL + (IDX) * 0x40UL)
#define RX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x20030UL + (IDX) * 0x40UL)
#define RX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x20038UL + (IDX) * 0x40UL)
#define TX_LOG_PAGE_VLD(IDX) (FZC_DMC + 0x40000UL + (IDX) * 0x200UL)
#define TX_LOG_MASK1(IDX) (FZC_DMC + 0x40008UL + (IDX) * 0x200UL)
#define TX_LOG_VAL1(IDX) (FZC_DMC + 0x40010UL + (IDX) * 0x200UL)
#define TX_LOG_MASK2(IDX) (FZC_DMC + 0x40018UL + (IDX) * 0x200UL)
#define TX_LOG_VAL2(IDX) (FZC_DMC + 0x40020UL + (IDX) * 0x200UL)
#define TX_LOG_PAGE_RELO1(IDX) (FZC_DMC + 0x40028UL + (IDX) * 0x200UL)
#define TX_LOG_PAGE_RELO2(IDX) (FZC_DMC + 0x40030UL + (IDX) * 0x200UL)
#define TX_LOG_PAGE_HDL(IDX) (FZC_DMC + 0x40038UL + (IDX) * 0x200UL)
#define RDC_RED_PARA(IDX) (FZC_DMC + 0x30000UL + (IDX) * 0x40UL)
#define RED_DIS_CNT(IDX) (FZC_DMC + 0x30008UL + (IDX) * 0x40UL)
#define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
#define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
#define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
#define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
#define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
#define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
#define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
#define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
#define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
#define RCRCFIG_B(IDX) (DMC + 0x00048UL + (IDX) * 0x200UL)
#define RCRSTAT_A(IDX) (DMC + 0x00050UL + (IDX) * 0x200UL)
#define RCRSTAT_B(IDX) (DMC + 0x00058UL + (IDX) * 0x200UL)
#define RCRSTAT_C(IDX) (DMC + 0x00060UL + (IDX) * 0x200UL)
#define RX_DMA_CTL_STAT(IDX) (DMC + 0x00070UL + (IDX) * 0x200UL)
#define RCR_FLSH(IDX) (DMC + 0x00078UL + (IDX) * 0x200UL)
#define RXMISC(IDX) (DMC + 0x00090UL + (IDX) * 0x200UL)
#define RX_DMA_CTL_STAT_DBG(IDX) (DMC + 0x00098UL + (IDX) * 0x200UL)
#define RX_DMA_ENT_MSK(IDX) (DMC + 0x00068UL + (IDX) * 0x200UL)
#define TX_RNG_CFIG(IDX) (DMC + 0x40000UL + (IDX) * 0x200UL)
#define TX_RING_HDL(IDX) (DMC + 0x40010UL + (IDX) * 0x200UL)
#define TX_RING_KICK(IDX) (DMC + 0x40018UL + (IDX) * 0x200UL)
#define TX_ENT_MSK(IDX) (DMC + 0x40020UL + (IDX) * 0x200UL)
#define TX_CS(IDX) (DMC + 0x40028UL + (IDX)*0x200UL)
#define TXDMA_MBH(IDX) (DMC + 0x40030UL + (IDX) * 0x200UL)
#define TXDMA_MBL(IDX) (DMC + 0x40038UL + (IDX) * 0x200UL)
#define TX_DMA_PRE_ST(IDX) (DMC + 0x40040UL + (IDX) * 0x200UL)
#define TX_RNG_ERR_LOGH(IDX) (DMC + 0x40048UL + (IDX) * 0x200UL)
#define TX_RNG_ERR_LOGL(IDX) (DMC + 0x40050UL + (IDX) * 0x200UL)
#define TDMC_INTR_DBG(IDX) (DMC + 0x40060UL + (IDX) * 0x200UL)
#define TX_CS_DBG(IDX) (DMC + 0x40068UL + (IDX) * 0x200UL)
#define TDMC_INJ_PAR_ERR(IDX) (DMC + 0x45040UL + (IDX) * 0x200UL)
#define TDMC_DBG_SEL(IDX) (DMC + 0x45080UL + (IDX) * 0x200UL)
#define TDMC_TRAINING_VECTOR(IDX) (DMC + 0x45088UL + (IDX) * 0x200UL)
#define TXC_PORT_DMA(IDX) (FZC_TXC + 0x20028UL + (IDX)*0x100UL)
#define ESPC_NCR(IDX) (FZC_PROM + 0x40020UL + (IDX)*0x8UL)
#define LD_IM0(IDX) (PIO_IMASK0 + 0x00000UL + (IDX) * 0x2000UL)
#define LD_IM1(IDX) (PIO_IMASK1 + 0x00000UL + (IDX) * 0x2000UL)
#define XPCS_STATUS(IDX) (FZC_MAC + 0x00040UL)
SUB_REG(MICIDX, IDX, 0x0000ffff)
SUB_REG(ADCIDX, IDX, 0x0000ffff)
SUB_REG(A_ADCIDX, IDX, 0x0000ffff)
SUB_REG(A_MICIDX, IDX, 0x0000ffff)
SUB_REG(FXIDX, IDX, 0x0000ffff)
#define SECURITY_HOOK_ACTIVE_KEY(HOOK, IDX) security_hook_active_##HOOK##_##IDX
#define LSM_STATIC_CALL(HOOK, IDX) lsm_static_call_##HOOK##_##IDX