arch/x86/coco/sev/core.c

1003

u64 msr = APIC_BASE_MSR + (reg >> 4);

arch/x86/coco/sev/core.c

977

u64 msr = APIC_BASE_MSR + (reg >> 4);

arch/x86/include/asm/apic.h

208

wrmsrq(APIC_BASE_MSR + (reg >> 4), v);

arch/x86/include/asm/apic.h

213

native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK);

arch/x86/include/asm/apic.h

223

rdmsrq(APIC_BASE_MSR + (reg >> 4), msr);

arch/x86/include/asm/apic.h

229

wrmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);

arch/x86/include/asm/apic.h

236

rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val);

arch/x86/kvm/lapic.c

3517

u32 reg = (msr - APIC_BASE_MSR) << 4;

arch/x86/kvm/lapic.c

3528

u32 reg = (msr - APIC_BASE_MSR) << 4;

arch/x86/kvm/lapic.h

26

#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))

arch/x86/kvm/svm/avic.c

138

svm_set_intercept_for_msr(vcpu, APIC_BASE_MSR + i,

arch/x86/kvm/svm/svm.h

677

return (msr >= APIC_BASE_MSR) &&

arch/x86/kvm/svm/svm.h

678

(msr < (APIC_BASE_MSR + 0x100));

arch/x86/kvm/vmx/vmx.c

4141

const int read_idx = APIC_BASE_MSR / BITS_PER_LONG_LONG;

arch/x86/kvm/x86.c

2261

case APIC_BASE_MSR + (APIC_ICR >> 4):

arch/x86/kvm/x86.c

4016

case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:

arch/x86/kvm/x86.c

4443

case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:

tools/testing/selftests/kvm/include/x86/apic.h

104

return wrmsr_safe(APIC_BASE_MSR + (reg >> 4), value);

tools/testing/selftests/kvm/include/x86/apic.h

112

fault, APIC_BASE_MSR + (reg >> 4), value);

tools/testing/selftests/kvm/include/x86/apic.h

121

APIC_BASE_MSR + (reg >> 4), value, fault);

tools/testing/selftests/kvm/include/x86/apic.h

99

return rdmsr(APIC_BASE_MSR + (reg >> 4));