arch/arm64/kvm/emulate-nested.c

429

.index = ICH_HCR_EL2,

arch/arm64/kvm/emulate-nested.c

435

.index = ICH_HCR_EL2,

arch/arm64/kvm/emulate-nested.c

441

.index = ICH_HCR_EL2,

arch/arm64/kvm/emulate-nested.c

447

.index = ICH_HCR_EL2,

arch/arm64/kvm/hyp/vgic-v3-sr.c

1080

ich_hcr = __vcpu_sys_reg(vcpu, ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

241

u64 val = read_gicreg(ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

246

write_gicreg(0, ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

261

write_gicreg(compute_ich_hcr(cpu_if), ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

337

write_gicreg(vgic_ich_hcr_trap_bits() | ICH_HCR_EL2_En, ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

362

write_gicreg(0, ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

797

hcr = read_gicreg(ICH_HCR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

799

write_gicreg(hcr, ICH_HCR_EL2);

arch/arm64/kvm/nested.c

1913

set_sysreg_masks(kvm, ICH_HCR_EL2, resx);

arch/arm64/kvm/sys_regs.c

3832

EL2_REG_VNCR_GICv3(ICH_HCR_EL2),

arch/arm64/kvm/vgic-sys-reg-v3.c

425

EL2_REG(ICH_HCR_EL2, ich_reg),

arch/arm64/kvm/vgic/vgic-v3-nested.c

184

hcr = __vcpu_sys_reg(vcpu, ICH_HCR_EL2);

arch/arm64/kvm/vgic/vgic-v3-nested.c

192

if (__vcpu_sys_reg(vcpu, ICH_HCR_EL2) & ICH_HCR_EL2_UIE) {

arch/arm64/kvm/vgic/vgic-v3-nested.c

273

u64 val = __vcpu_sys_reg(vcpu, ICH_HCR_EL2);

arch/arm64/kvm/vgic/vgic-v3-nested.c

314

__vcpu_rmw_sys_reg(vcpu, ICH_HCR_EL2, &=, ~ICH_HCR_EL2_EOIcount);

arch/arm64/kvm/vgic/vgic-v3-nested.c

315

__vcpu_rmw_sys_reg(vcpu, ICH_HCR_EL2, |=, read_sysreg_s(SYS_ICH_HCR_EL2) & ICH_HCR_EL2_EOIcount);

arch/arm64/kvm/vgic/vgic-v3-nested.c

329

s_cpu_if->vgic_hcr = __vcpu_sys_reg(vcpu, ICH_HCR_EL2);

arch/arm64/kvm/vgic/vgic-v3-nested.c

404

level = (__vcpu_sys_reg(vcpu, ICH_HCR_EL2) & ICH_HCR_EL2_En) && vgic_v3_get_misr(vcpu);