APIC_TASKPRI
case APIC_TASKPRI:
case APIC_TASKPRI:
value = apic_read(APIC_TASKPRI);
apic_write(APIC_TASKPRI, value);
apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
v = apic_read(APIC_TASKPRI);
case APIC_TASKPRI:
case APIC_TASKPRI:
return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
case APIC_TASKPRI:
APIC_REG_MASK(APIC_TASKPRI) |
case APIC_TASKPRI:
tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
X2APIC_MSR(APIC_TASKPRI),
u32 vtpr = vapic ? (*(u32 *)(vapic + APIC_TASKPRI)) >> 4 : 0;
X2APIC_MSR(APIC_TASKPRI),
case X2APIC_MSR(APIC_TASKPRI):
vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,
data->halter_tpr = xapic_read_reg(APIC_TASKPRI);
return GET_APIC_PRI(*((u32 *)&xapic->regs[APIC_TASKPRI]));
u32 *taskpri = (u32 *)&xapic->regs[APIC_TASKPRI];
taskpri = x2apic_read_reg(APIC_TASKPRI);
taskpri = xapic_read_reg(APIC_TASKPRI);