ICEREG
old_cmd = inb(ICEREG(ice, AC97_CMD));
outb(reg, ICEREG(ice, AC97_INDEX));
outw(val, ICEREG(ice, AC97_DATA));
outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
old_cmd = inb(ICEREG(ice, AC97_CMD));
outb(reg, ICEREG(ice, AC97_INDEX));
outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
return inw(ICEREG(ice, AC97_DATA));
outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
return inb(ICEREG(ice, I2C_DATA));
if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
outb(0, ICEREG(ice, AC97_CMD));
ICEREG(ice, IRQMASK));
outb(0xff, ICEREG(ice, IRQMASK));
ICEREG(ice, MPU1_CTRL),
ICEREG(ice, MPU2_CTRL),
inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
status = inb(ICEREG(ice, IRQSTAT));
outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
outw(buf_size, ICEREG(ice, CONCAP_COUNT));
ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
outb(addr, ICEREG(ice, INDEX));
outb(data, ICEREG(ice, DATA));
outb(addr, ICEREG(ice, INDEX));
return inb(ICEREG(ice, DATA));