IB_WR_REG_MR
reg->reg_wr.wr.opcode = IB_WR_REG_MR;
case IB_WR_REG_MR:
case IB_WR_REG_MR: {
case IB_WR_REG_MR:
case IB_WR_REG_MR:
[IB_WR_REG_MR] = {
if (wqe->wr.opcode == IB_WR_REG_MR ||
if (wqe->wr.opcode == IB_WR_REG_MR ||
[IB_WR_REG_MR] = IB_WC_REG_MR
case IB_WR_REG_MR:
} else if (wr->opcode != IB_WR_REG_MR) {
case IB_WR_REG_MR:
return op == IB_WR_LOCAL_INV || op == IB_WR_REG_MR;
case IB_WR_REG_MR: {
case IB_WR_REG_MR:
[IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
case IB_WR_REG_MR:
if (wr->opcode == IB_WR_REG_MR ||
[IB_WR_REG_MR] = MLX5_OPCODE_UMR,
qp->sq.wr_data[idx] = IB_WR_REG_MR;
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR: return IB_WC_REG_MR;
[IB_WR_REG_MR] = {
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
case IB_WR_REG_MR:
wr->wr.opcode = IB_WR_REG_MR;
.wr.opcode = IB_WR_REG_MR,
.wr.opcode = IB_WR_REG_MR,
rwr.wr.opcode = IB_WR_REG_MR;
rwr.wr.opcode = IB_WR_REG_MR;
rwr[mri].wr.opcode = IB_WR_REG_MR;
wr.wr.opcode = IB_WR_REG_MR;
req->reg_wr.wr.opcode = IB_WR_REG_MR;
reg_wr->wr.opcode = IB_WR_REG_MR;
reg_wr.wr.opcode = IB_WR_REG_MR;
lnk->wr_reg.wr.opcode = IB_WR_REG_MR;
mr->mr_regwr.wr.opcode = IB_WR_REG_MR;
mr->mr_regwr.wr.opcode = IB_WR_REG_MR;