IB_WR_MASKED_ATOMIC_CMP_AND_SWP
case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
[IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
[IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
send->s_atomic_wr.wr.opcode = IB_WR_MASKED_ATOMIC_CMP_AND_SWP;