IB_WR_ATOMIC_CMP_AND_SWP
} else if (user_wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
if (op == IB_WR_ATOMIC_CMP_AND_SWP) {
[IB_WR_ATOMIC_CMP_AND_SWP] = {
opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
((wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
case IB_WR_ATOMIC_CMP_AND_SWP:
if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
case IB_WR_ATOMIC_CMP_AND_SWP:
[IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
case IB_WR_ATOMIC_CMP_AND_SWP:
if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
case IB_WR_ATOMIC_CMP_AND_SWP:
[IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
[IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
case IB_WR_ATOMIC_CMP_AND_SWP:
if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
case IB_WR_ATOMIC_CMP_AND_SWP:
[IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP)
case IB_WR_ATOMIC_CMP_AND_SWP:
if (wqe->wr.opcode != IB_WR_ATOMIC_CMP_AND_SWP &&
case IB_WR_ATOMIC_CMP_AND_SWP: return IB_WC_COMP_SWAP;
[IB_WR_ATOMIC_CMP_AND_SWP] = {
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP:
case IB_WR_ATOMIC_CMP_AND_SWP: