IA32_EDX
EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX));
EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r0[1]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r3[0]));
EMIT3(0x39, add_2reg(0x40, IA32_EAX, IA32_EDX),
EMIT2(0x85, add_2reg(0xC0, IA32_EDX, IA32_EDX));
EMIT3(0x8B, add_2reg(0x40, IA32_EDX, IA32_EDX),
EMIT3(0x83, add_1reg(0xC0, IA32_EDX), PROLOGUE_SIZE);
const u8 arg_regs[] = { IA32_EAX, IA32_EDX, IA32_ECX };
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EDX));
EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
IA32_EDX),
IA32_EDX));
IA32_EDX),
IA32_EDX));
EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EDX));
add_2reg(0x80, IA32_EAX, IA32_EDX),
IA32_EDX),
add_2reg(0xC0, dst_hi, IA32_EDX));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
IA32_EDX),
u8 dreg_hi = IA32_EDX;
IA32_EDX),
u8 dreg_hi = IA32_EDX;
IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT2(0x31, add_2reg(0xC0, IA32_EDX, IA32_EDX));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT2(0x89, add_2reg(0xC0, dst, IA32_EDX));
u8 dreg = dstk ? IA32_EDX : dst;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(dst));
u8 sreg = IA32_EDX;
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EDX), val);
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),