IA32_EBP
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_hi));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX),
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_hi));
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX),
EMIT3(0x83, add_1reg(0xE8, IA32_EBP), SCRATCH_SIZE + 12);
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBP), STACK_VAR(fplo));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(fphi));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(r1[1]));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[0]));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r0[0]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r0[1]));
EMIT3(0x83, add_1reg(0xC0, IA32_EBP), SCRATCH_SIZE + 12);
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), -12);
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ESI), -8);
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDI), -4);
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r2[0]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r3[0]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0]));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_hi));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_lo));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_lo));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, *cur_arg_reg++),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, *cur_arg_reg++),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0xC7, add_1reg(0x40, IA32_EBP),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
add_2reg(0x40, IA32_EBP,
EMIT3_off32(0xC7, add_1reg(0x40, IA32_EBP),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
add_2reg(0x40, IA32_EBP,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, sreg), STACK_VAR(dst));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg), STACK_VAR(dst));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(dst));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),