IA32_EAX
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x8B, add_2reg(0xC0, dst_hi, IA32_EAX));
EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EAX));
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX));
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), hi);
EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX));
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EAX));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r0[0]));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r2[0]));
EMIT3(0x39, add_2reg(0x40, IA32_EAX, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
const u8 arg_regs[] = { IA32_EAX, IA32_EDX, IA32_ECX };
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
EMIT2(add_1reg(0x40, IA32_EAX), insn->off);
EMIT1_off32(add_1reg(0x80, IA32_EAX),
EMIT2_off32(0xC7, add_1reg(0x80, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
EMIT2(add_2reg(0x40, IA32_EAX,
EMIT1(add_2reg(0x80, IA32_EAX,
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EAX));
EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
add_2reg(0x80, IA32_EAX, IA32_EDX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x33, add_2reg(0xC0, IA32_EAX, IA32_EAX));
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = IA32_EAX;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = IA32_EAX;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 sreg = sstk ? IA32_EAX : src;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
EMIT2(0x8B, add_2reg(0xC0, dst, IA32_EAX));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x89, add_2reg(0xC0, dst, IA32_EAX));
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x8B, add_2reg(0xC0, dst, IA32_EAX));
EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
EMIT2(0x89, add_2reg(0xC0, dst, IA32_EAX));
u8 dreg = dstk ? IA32_EAX : dst;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
u8 sreg = sstk ? IA32_EAX : src;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
u8 dreg = dstk ? IA32_EAX : dst;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),