I3
REG_OFFSET_NAME("i3", I3),
emit_reg_move(I3, O3, ctx);
val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);
val = REG_CLR_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);
val = REG_SET_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);
val = REG_CLR_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);
{.dest = TRIGGER_LINE(2), .src = I3(rgout0_src1,
{.dest = TRIGGER_LINE(3), .src = I3(rgout0_src1,
{.dest = TRIGGER_LINE(1), .src = I3(rgout0_src0,
func(I3) \
func(I3) \
#define __FP_FRAC_SET_4(X,I3,I2,I1,I0) \
(X##_f[3] = I3, X##_f[2] = I2, X##_f[1] = I1, X##_f[0] = I0)