HW_STRAP1
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
SIG_EXPR_DECL_SINGLE(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14));
#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
#define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0)
SIG_EXPR_LIST_DECL_SINGLE(Y21, USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
#define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4)
#define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
#define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
#define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)