HVS_WRITE
HVS_WRITE(hvs->vc4->gen == VC4_GEN_6_C ? SCALER6_ ## offset : SCALER6D_ ## offset, val)
HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
HVS_WRITE(SCALER_DISPBKGNDX(channel),
HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx);
HVS_WRITE(SCALER_DISPCTRL, dispctrl);
HVS_WRITE(SCALER_DISPSTAT,
HVS_WRITE(SCALER_DISPCTRL, dispctrl);
HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
HVS_WRITE(SCALER_DISPCTRL, dispctrl);
HVS_WRITE(SCALER_DISPECTRL,
HVS_WRITE(SCALER_DISPCTRL,
HVS_WRITE(SCALER_DISPEOLN,
HVS_WRITE(SCALER_DISPDITHER,
HVS_WRITE(SCALER_DISPCTRL, dispctrl);
HVS_WRITE(SCALER6_CONTROL,
HVS_WRITE(SCALER6(PRI_MAP0), 0xffffffff);
HVS_WRITE(SCALER6(PRI_MAP1), 0xffffffff);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C03(i), coeffs->csc[0][3]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C04(i), coeffs->csc[0][4]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[1][0]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C11(i), coeffs->csc[1][1]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C12(i), coeffs->csc[1][2]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C13(i), coeffs->csc[1][3]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C14(i), coeffs->csc[1][4]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C20(i), coeffs->csc[2][0]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C21(i), coeffs->csc[2][1]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C22(i), coeffs->csc[2][2]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C23(i), coeffs->csc[2][3]);
HVS_WRITE(CFC1_N_MA_CSC_COEFF_C24(i), coeffs->csc[2][4]);
HVS_WRITE(CFC1_N_NL_CSC_CTRL(i), BIT(15));
HVS_WRITE(SCALER_PI_CMP_CSC_RED0(i), 0x1f002566);
HVS_WRITE(SCALER_PI_CMP_CSC_RED1(i), 0x3994);
HVS_WRITE(SCALER_PI_CMP_CSC_RED_CLAMP(i), 0xfff00000);
HVS_WRITE(SCALER_PI_CMP_CSC_CFG(i), 0x1);
HVS_WRITE(SCALER_PI_CMP_CSC_GREEN0(i), 0x18002566);
HVS_WRITE(SCALER_PI_CMP_CSC_GREEN1(i), 0xf927eee2);
HVS_WRITE(SCALER_PI_CMP_CSC_GREEN_CLAMP(i), 0xfff00000);
HVS_WRITE(SCALER_PI_CMP_CSC_BLUE0(i), 0x18002566);
HVS_WRITE(SCALER_PI_CMP_CSC_BLUE1(i), 0x43d80000);
HVS_WRITE(SCALER_PI_CMP_CSC_BLUE_CLAMP(i), 0xfff00000);
HVS_WRITE(SCALER_DISPBASE2, reg);
HVS_WRITE(SCALER_DISPBASE1, reg);
HVS_WRITE(SCALER_DISPBASE0, reg);
HVS_WRITE(SCALER_DISPBASE2, reg);
HVS_WRITE(SCALER_DISPBASE1, reg);
HVS_WRITE(SCALER_DISPBASE0, reg);
HVS_WRITE(SCALER6_DISPX_COB(2),
HVS_WRITE(SCALER6_DISPX_COB(1),
HVS_WRITE(SCALER6_DISPX_COB(0),
HVS_WRITE(SCALER_GAMADDR,
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
HVS_WRITE(SCALER6_DISPX_CTRL0(chan), SCALER6_DISPX_CTRL0_RESET);
HVS_WRITE(SCALER6_DISPX_CTRL1(chan),
HVS_WRITE(SCALER6_DISPX_CTRL0(chan),
HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
HVS_WRITE(SCALER6_DISPX_CTRL0(chan),
HVS_WRITE(SCALER6_DISPX_CTRL0(chan),
HVS_WRITE(SCALER6_DISPX_LPTRS(vc4_state->assigned_channel),
HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
HVS_WRITE(SCALER_OLEDCOEF2,
HVS_WRITE(SCALER_OLEDCOEF1,
HVS_WRITE(SCALER_OLEDCOEF0,
HVS_WRITE(SCALER_OLEDOFFS,
HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
HVS_WRITE(SCALER_DISPECTRL,
HVS_WRITE(SCALER_DISPCTRL,
HVS_WRITE(SCALER_DISPEOLN,
HVS_WRITE(SCALER_DISPDITHER,
HVS_WRITE(SCALER6_CONTROL,