drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1211

case HUBP_CLK_CNTL:

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3586

seq_state->steps[*seq_state->num_steps].func = HUBP_CLK_CNTL;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1070

REG_GET(HUBP_CLK_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1304

REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

107

SRI(HUBP_CLK_CNTL, HUBP, id),\

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

255

uint32_t HUBP_CLK_CNTL; \

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1121

REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1307

REG_GET(HUBP_CLK_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

500

reg_state->clk_cntl = REG_READ(HUBP_CLK_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

45

REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

992

REG_GET(HUBP_CLK_CNTL,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

1147

SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

106

SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \