HSTATUS
hstatus = ioread32(hcr_base + HSTATUS);
hstatus = ioread32(hcr_base + HSTATUS);
interrupt_enables = ioread32(hcr_base + HSTATUS);
iowrite32(interrupt_enables, hcr_base + HSTATUS);
temp = ioread32(hcr_base + HSTATUS);
iowrite32((temp & 0x3F), hcr_base + HSTATUS);
ioread32(hcr_base + HSTATUS), ioread32(hcr_base + HCONTROL));
ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
temp = ioread32(hcr_base + HSTATUS);
iowrite32((temp & 0x3F), hcr_base + HSTATUS);
ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
ioread32(hcr_base + HSTATUS),
temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
ioread32(hcr_base + HSTATUS),
temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
ioread32(hcr_base + HSTATUS));
temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
ioread32(hcr_base + HSTATUS),
gru_gamir(cb, EOP_IR_CLR, HSTATUS(mqd->mq_gpa, half), XTYPE_DW, IMA);
gru_gamir(cb, EOP_IR_INC, HSTATUS(mqd->mq_gpa, half),
gru_gamir(cb, EOP_IR_INC, HSTATUS(mqd->mq_gpa, half), XTYPE_DW,