drivers/clk/rockchip/clk-cpu.c

199

writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],

drivers/clk/rockchip/clk-cpu.c

209

writel(HIWORD_UPDATE(reg_data->mux_core_alt,

drivers/clk/rockchip/clk-cpu.c

214

writel(HIWORD_UPDATE(reg_data->mux_core_alt,

drivers/clk/rockchip/clk-cpu.c

251

writel(HIWORD_UPDATE(reg_data->mux_core_main,

drivers/clk/rockchip/clk-cpu.c

256

writel(HIWORD_UPDATE(reg_data->mux_core_main,

drivers/clk/rockchip/clk-cpu.c

265

writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],

drivers/clk/rockchip/clk-inverter.c

49

writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift),

drivers/clk/rockchip/clk-mmc-phase.c

145

raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift);

drivers/clk/rockchip/clk-pll.c

1012

writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),

drivers/clk/rockchip/clk-pll.c

1023

writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0),

drivers/clk/rockchip/clk-pll.c

221

writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,

drivers/clk/rockchip/clk-pll.c

223

HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,

drivers/clk/rockchip/clk-pll.c

227

writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,

drivers/clk/rockchip/clk-pll.c

229

HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,

drivers/clk/rockchip/clk-pll.c

231

HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,

drivers/clk/rockchip/clk-pll.c

279

writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),

drivers/clk/rockchip/clk-pll.c

290

writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,

drivers/clk/rockchip/clk-pll.c

454

writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),

drivers/clk/rockchip/clk-pll.c

458

writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,

drivers/clk/rockchip/clk-pll.c

460

HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,

drivers/clk/rockchip/clk-pll.c

464

writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,

drivers/clk/rockchip/clk-pll.c

467

writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,

drivers/clk/rockchip/clk-pll.c

472

writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),

drivers/clk/rockchip/clk-pll.c

514

writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),

drivers/clk/rockchip/clk-pll.c

525

writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,

drivers/clk/rockchip/clk-pll.c

703

writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,

drivers/clk/rockchip/clk-pll.c

707

writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,

drivers/clk/rockchip/clk-pll.c

709

HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,

drivers/clk/rockchip/clk-pll.c

711

HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,

drivers/clk/rockchip/clk-pll.c

721

writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,

drivers/clk/rockchip/clk-pll.c

763

writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),

drivers/clk/rockchip/clk-pll.c

774

writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,

drivers/clk/rockchip/clk-pll.c

955

writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN,

drivers/clk/rockchip/clk-pll.c

960

writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT),

drivers/clk/rockchip/clk-pll.c

963

writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) |

drivers/clk/rockchip/clk-pll.c

964

HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT),

drivers/clk/rockchip/clk-pll.c

967

writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),

drivers/clk/rockchip/clk-pll.c

971

writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),

drivers/clk/rockchip/clk-px30.c

81

.val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \

drivers/clk/rockchip/clk-px30.c

83

HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \

drivers/clk/rockchip/clk-rk3036.c

457

writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),

drivers/clk/rockchip/clk-rk3036.c

86

.val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \

drivers/clk/rockchip/clk-rk3128.c

83

.val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \

drivers/clk/rockchip/clk-rk3128.c

85

HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \

drivers/clk/rockchip/clk-rk3188.c

112

.val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \

drivers/clk/rockchip/clk-rk3188.c

118

.val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3188.c

120

HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \

drivers/clk/rockchip/clk-rk3188.c

122

HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \

drivers/clk/rockchip/clk-rk3188.c

124

HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \

drivers/clk/rockchip/clk-rk3188.c

164

.val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\

drivers/clk/rockchip/clk-rk3228.c

84

.val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \

drivers/clk/rockchip/clk-rk3228.c

86

HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \

drivers/clk/rockchip/clk-rk3288.c

138

.val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \

drivers/clk/rockchip/clk-rk3288.c

140

HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \

drivers/clk/rockchip/clk-rk3288.c

146

.val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \

drivers/clk/rockchip/clk-rk3288.c

148

HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \

drivers/clk/rockchip/clk-rk3288.c

150

HIWORD_UPDATE(_pclk_dbg_pre, \

drivers/clk/rockchip/clk-rk3308.c

77

.val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \

drivers/clk/rockchip/clk-rk3308.c

79

HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK, \

drivers/clk/rockchip/clk-rk3328.c

96

.val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \

drivers/clk/rockchip/clk-rk3328.c

98

HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \

drivers/clk/rockchip/clk-rk3368.c

188

.val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \

drivers/clk/rockchip/clk-rk3368.c

194

.val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \

drivers/clk/rockchip/clk-rk3368.c

196

HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \

drivers/clk/rockchip/clk-rk3399.c

325

.val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \

drivers/clk/rockchip/clk-rk3399.c

331

.val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \

drivers/clk/rockchip/clk-rk3399.c

333

HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \

drivers/clk/rockchip/clk-rk3506.c

71

.val = HIWORD_UPDATE(_aclk_core_div, RK3506_DIV_ACLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3506.c

78

.val = HIWORD_UPDATE(_pclk_core_div, RK3506_DIV_PCLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3528.c

61

.val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \

drivers/clk/rockchip/clk-rk3528.c

68

.val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \

drivers/clk/rockchip/clk-rk3568.c

122

.val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \

drivers/clk/rockchip/clk-rk3568.c

124

HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3568.c

126

HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3568.c

133

.val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3568.c

140

.val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3568.c

142

HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3568.c

149

.val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3568.c

151

HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \

drivers/clk/rockchip/clk-rk3576.c

119

.val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_BIGCORE_DIV_MASK, \

drivers/clk/rockchip/clk-rk3576.c

126

.val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_LITCORE_DIV_MASK, \

drivers/clk/rockchip/clk-rk3576.c

133

.val = HIWORD_UPDATE(_pclkdbg - 1, RK3576_PCLK_DBG_LITCORE_DIV_MASK, \

drivers/clk/rockchip/clk-rk3576.c

140

.val = HIWORD_UPDATE(_ccisel, RK3576_ACLK_CCI_MUX_MASK, \

drivers/clk/rockchip/clk-rk3576.c

142

HIWORD_UPDATE(_div - 1, RK3576_ACLK_CCI_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

130

.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \

drivers/clk/rockchip/clk-rk3588.c

132

HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

139

.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \

drivers/clk/rockchip/clk-rk3588.c

146

.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \

drivers/clk/rockchip/clk-rk3588.c

148

HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

155

.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \

drivers/clk/rockchip/clk-rk3588.c

162

.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \

drivers/clk/rockchip/clk-rk3588.c

164

HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \

drivers/clk/rockchip/clk-rk3588.c

171

.val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \

drivers/clk/rockchip/clk-rk3588.c

173

HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

180

.val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

182

HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

184

HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

191

.val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

198

.val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \

drivers/clk/rockchip/clk-rk3588.c

200

HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK, \

drivers/clk/rockchip/clk-rv1108.c

75

.val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\

drivers/clk/rockchip/clk-rv1126.c

89

.val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \

drivers/clk/rockchip/clk-rv1126.c

91

HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \

drivers/clk/rockchip/clk-rv1126b.c

49

.val = HIWORD_UPDATE(_aclk_core - 1, RV1126B_DIV_ACLK_CORE_MASK, \

drivers/clk/rockchip/clk-rv1126b.c

56

.val = HIWORD_UPDATE(_pclk_dbg - 1, RV1126B_DIV_PCLK_CORE_MASK, \

drivers/mmc/host/sdhci-of-arasan.c

340

HIWORD_UPDATE(val, GENMASK(width, 0),

drivers/phy/rockchip/phy-rockchip-emmc.c

109

HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,

drivers/phy/rockchip/phy-rockchip-emmc.c

114

HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,

drivers/phy/rockchip/phy-rockchip-emmc.c

167

HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,

drivers/phy/rockchip/phy-rockchip-emmc.c

190

HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,

drivers/phy/rockchip/phy-rockchip-emmc.c

196

HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,

drivers/phy/rockchip/phy-rockchip-emmc.c

291

HIWORD_UPDATE(rk_phy->drive_impedance,

drivers/phy/rockchip/phy-rockchip-emmc.c

298

HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,

drivers/phy/rockchip/phy-rockchip-emmc.c

305

HIWORD_UPDATE(rk_phy->output_tapdelay_select,

drivers/phy/rockchip/phy-rockchip-emmc.c

312

HIWORD_UPDATE(rk_phy->enable_strobe_pulldown,

drivers/phy/rockchip/phy-rockchip-inno-csidphy.c

164

HIWORD_UPDATE(value, reg->mask, reg->shift));

sound/soc/rockchip/rockchip_i2s_tdm.h

293

#define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12)

sound/soc/rockchip/rockchip_i2s_tdm.h

294

#define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12)

sound/soc/rockchip/rockchip_i2s_tdm.h

295

#define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)

sound/soc/rockchip/rockchip_i2s_tdm.h

296

#define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)

sound/soc/rockchip/rockchip_i2s_tdm.h

305

#define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)

sound/soc/rockchip/rockchip_i2s_tdm.h

306

#define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)

sound/soc/rockchip/rockchip_i2s_tdm.h

307

#define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0)

sound/soc/rockchip/rockchip_i2s_tdm.h

308

#define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0)

sound/soc/rockchip/rockchip_i2s_tdm.h

317

#define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 10, 10)

sound/soc/rockchip/rockchip_i2s_tdm.h

318

#define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 10, 10)

sound/soc/rockchip/rockchip_i2s_tdm.h

319

#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 9, 9)

sound/soc/rockchip/rockchip_i2s_tdm.h

320

#define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 9, 9)

sound/soc/rockchip/rockchip_i2s_tdm.h

321

#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 8, 8)

sound/soc/rockchip/rockchip_i2s_tdm.h

322

#define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 8, 8)

sound/soc/rockchip/rockchip_i2s_tdm.h

323

#define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)

sound/soc/rockchip/rockchip_i2s_tdm.h

324

#define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)

sound/soc/rockchip/rockchip_i2s_tdm.h

325

#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 1, 1)

sound/soc/rockchip/rockchip_i2s_tdm.h

326

#define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 1, 1)

sound/soc/rockchip/rockchip_i2s_tdm.h

327

#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 0, 0)

sound/soc/rockchip/rockchip_i2s_tdm.h

328

#define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 0, 0)

sound/soc/rockchip/rockchip_i2s_tdm.h

351

#define RK3568_I2S1_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)

sound/soc/rockchip/rockchip_i2s_tdm.h

352

#define RK3568_I2S1_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)

sound/soc/rockchip/rockchip_i2s_tdm.h

360

#define RK3568_I2S3_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 15, 15)

sound/soc/rockchip/rockchip_i2s_tdm.h

361

#define RK3568_I2S3_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 15, 15)

sound/soc/rockchip/rockchip_i2s_tdm.h

362

#define RK3568_I2S3_SCLK_SRC_FROM_TX HIWORD_UPDATE(1, 7, 7)

sound/soc/rockchip/rockchip_i2s_tdm.h

363

#define RK3568_I2S3_SCLK_SRC_FROM_RX HIWORD_UPDATE(0, 7, 7)

sound/soc/rockchip/rockchip_i2s_tdm.h

364

#define RK3568_I2S3_LRCK_SRC_FROM_TX HIWORD_UPDATE(1, 6, 6)

sound/soc/rockchip/rockchip_i2s_tdm.h

365

#define RK3568_I2S3_LRCK_SRC_FROM_RX HIWORD_UPDATE(0, 6, 6)

sound/soc/rockchip/rockchip_i2s_tdm.h

381

#define RK3568_I2S3_MCLK_IE HIWORD_UPDATE(0, 3, 3)

sound/soc/rockchip/rockchip_i2s_tdm.h

382

#define RK3568_I2S3_MCLK_OE HIWORD_UPDATE(1, 3, 3)

sound/soc/rockchip/rockchip_i2s_tdm.h

383

#define RK3568_I2S2_MCLK_IE HIWORD_UPDATE(0, 2, 2)

sound/soc/rockchip/rockchip_i2s_tdm.h

384

#define RK3568_I2S2_MCLK_OE HIWORD_UPDATE(1, 2, 2)

sound/soc/rockchip/rockchip_i2s_tdm.h

385

#define RK3568_I2S1_MCLK_TX_IE HIWORD_UPDATE(0, 1, 1)

sound/soc/rockchip/rockchip_i2s_tdm.h

386

#define RK3568_I2S1_MCLK_TX_OE HIWORD_UPDATE(1, 1, 1)

sound/soc/rockchip/rockchip_i2s_tdm.h

387

#define RK3568_I2S1_MCLK_RX_IE HIWORD_UPDATE(0, 0, 0)

sound/soc/rockchip/rockchip_i2s_tdm.h

388

#define RK3568_I2S1_MCLK_RX_OE HIWORD_UPDATE(1, 0, 0)

sound/soc/rockchip/rockchip_i2s_tdm.h

391

#define RV1126_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 9, 9)

sound/soc/rockchip/rockchip_i2s_tdm.h

392

#define RV1126_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 9, 9)