drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

143

writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

144

HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

150

reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

184

reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

256

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

257

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

258

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

259

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

260

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

261

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

262

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

342

writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

343

HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

346

writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

347

HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

380

writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

381

HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

384

writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

385

HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

388

writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

389

HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

392

writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

393

HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

396

val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

397

val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

478

reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c

187

control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c

188

control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);