drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

145

hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_REQ, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

146

ret = readl_poll_timeout(dp->base + HIBMC_DP_AUX_REQ, val,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

158

hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_SEL, 0x0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

159

hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIMEOUT, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

160

hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE_NUM,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

217

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_SEL, 0x0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

218

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIMEOUT, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

219

hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE_NUM, 0x9);