drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

126

writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

127

HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

133

reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

167

reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

243

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

244

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

245

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

246

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

247

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

248

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

249

pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

332

writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

333

HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

336

writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

337

HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

370

writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

371

HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

374

writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

375

HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

378

writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

379

HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

382

writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

383

HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

386

val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

387

val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

468

reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c

186

control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c

187

control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);