drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

32

u8 train_set[HIBMC_DP_LANE_NUM_MAX];

drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h

71

int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC_DP_LANE_NUM_MAX]);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

141

u8 train_set[HIBMC_DP_LANE_NUM_MAX] = {0};

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

148

if (memcmp(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX)) {

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

149

memcpy(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

335

if (dp->link.cap.lanes > HIBMC_DP_LANE_NUM_MAX)

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

336

dp->link.cap.lanes = HIBMC_DP_LANE_NUM_MAX;

drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c

11

int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC_DP_LANE_NUM_MAX])

drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c

21

for (i = 0; i < HIBMC_DP_LANE_NUM_MAX; i++) {