drivers/clk/meson/g12a.c

2747

.reg_off = HHI_VID_PLL_CLK_DIV,

drivers/clk/meson/g12a.c

2752

.reg_off = HHI_VID_PLL_CLK_DIV,

drivers/clk/meson/g12a.c

2773

.offset = HHI_VID_PLL_CLK_DIV,

drivers/clk/meson/g12a.c

2792

.offset = HHI_VID_PLL_CLK_DIV,

drivers/clk/meson/gxbb.c

1880

.reg_off = HHI_VID_PLL_CLK_DIV,

drivers/clk/meson/gxbb.c

1885

.reg_off = HHI_VID_PLL_CLK_DIV,

drivers/clk/meson/gxbb.c

1923

.offset = HHI_VID_PLL_CLK_DIV,

drivers/clk/meson/gxbb.c

1942

.offset = HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

140

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);

drivers/gpu/drm/meson/meson_vclk.c

141

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);

drivers/gpu/drm/meson/meson_vclk.c

204

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

208

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

211

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

213

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

215

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

219

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

221

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

223

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

226

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,

drivers/gpu/drm/meson/meson_vclk.c

231

regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,