drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1595

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1628

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1629

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1630

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1471

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1472

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1473

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

644

REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

649

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

142

SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

143

SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

144

SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

145

SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

681

uint32_t HDMI_VBI_PACKET_CONTROL;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

75

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

582

REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

587

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

158

uint32_t HDMI_VBI_PACKET_CONTROL;

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

65

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

690

REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

696

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

67

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

251

REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

257

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

68

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

209

REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

215

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

197

REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

203

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

66

SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

211

REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

217

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c

138

REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c

144

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

281

SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

99

SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

198

SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

245

SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

223

SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \

drivers/gpu/drm/radeon/evergreen_hdmi.c

313

WREG32(HDMI_VBI_PACKET_CONTROL + offset,