drivers/clk/meson/gxbb.c

214

.reg_off = HHI_HDMI_PLL_CNTL2,

drivers/clk/meson/gxbb.c

268

.reg_off = HHI_HDMI_PLL_CNTL2,

drivers/clk/meson/gxbb.c

300

.offset = HHI_HDMI_PLL_CNTL2,

drivers/clk/meson/gxbb.c

318

.offset = HHI_HDMI_PLL_CNTL2,

drivers/clk/meson/gxbb.c

336

.offset = HHI_HDMI_PLL_CNTL2,

drivers/gpu/drm/meson/meson_vclk.c

247

regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);

drivers/gpu/drm/meson/meson_vclk.c

260

regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);

drivers/gpu/drm/meson/meson_vclk.c

277

regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000);

drivers/gpu/drm/meson/meson_vclk.c

499

regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,

drivers/gpu/drm/meson/meson_vclk.c

502

regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,

drivers/gpu/drm/meson/meson_vclk.c

519

regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);

drivers/gpu/drm/meson/meson_vclk.c

542

regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);

drivers/gpu/drm/meson/meson_vclk.c

587

regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,

drivers/gpu/drm/meson/meson_vclk.c

598

regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,

drivers/gpu/drm/meson/meson_vclk.c

609

regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,