arch/arm64/include/asm/kvm_host.h

1645

case HFGWTR_EL2:

arch/arm64/include/asm/kvm_host.h

1672

case HFGWTR_EL2: \

arch/arm64/kvm/config.c

1478

case HFGWTR_EL2:

arch/arm64/kvm/config.c

1548

case HFGWTR_EL2:

arch/arm64/kvm/config.c

1595

__compute_fgt(vcpu, HFGWTR_EL2);

arch/arm64/kvm/config.c

1598

*vcpu_fgt(vcpu, HFGWTR_EL2) |= HFGWTR_EL2_TCR_EL1;

arch/arm64/kvm/emulate-nested.c

2528

fgtreg = is_read ? HFGRTR_EL2 : HFGWTR_EL2;

arch/arm64/kvm/hyp/include/hyp/switch.h

218

__activate_fgt(hctxt, vcpu, HFGWTR_EL2);

arch/arm64/kvm/hyp/include/hyp/switch.h

250

__deactivate_fgt(hctxt, vcpu, HFGWTR_EL2);

arch/arm64/kvm/hyp/vgic-v3-sr.c

1089

(__vcpu_sys_reg(vcpu, HFGWTR_EL2) & HFGWTR_EL2_ICC_IGRPENn_EL1))

arch/arm64/kvm/hyp/vgic-v3-sr.c

1110

(__vcpu_sys_reg(vcpu, HFGWTR_EL2) & HFGWTR_EL2_ICC_IGRPENn_EL1))

arch/arm64/kvm/nested.c

1744

resx = get_reg_fixed_bits(kvm, HFGWTR_EL2);

arch/arm64/kvm/nested.c

1745

set_sysreg_masks(kvm, HFGWTR_EL2, resx);

arch/arm64/kvm/sys_regs.c

3650

EL2_REG_VNCR_FILT(HFGWTR_EL2, fgt_visibility),

tools/testing/selftests/kvm/arm64/get-reg-list.c

54

REG_FEAT(HFGWTR_EL2, ID_AA64MMFR0_EL1, FGT, IMP),

tools/testing/selftests/kvm/arm64/get-reg-list.c

729

SYS_REG(HFGWTR_EL2),