drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1493

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1501

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1322

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

186

SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

686

uint32_t HDMI_ACR_44_0;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

80

SRI(HDMI_ACR_44_0, DIG, id),\

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1293

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

163

uint32_t HDMI_ACR_44_0;

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

70

SRI(HDMI_ACR_44_0, DIG, id),\

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

801

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

72

SRI(HDMI_ACR_44_0, DIG, id),\

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

73

SRI(HDMI_ACR_44_0, DIG, id),\

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

71

SRI(HDMI_ACR_44_0, DIG, id),\

drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c

372

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

285

SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h

104

SRI_ARR(HDMI_ACR_44_0, DIG, id),\

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

202

SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h

249

SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h

227

SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \

drivers/gpu/drm/radeon/evergreen_hdmi.c

92

WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));