AML_UART_CONTROL
val = readl(port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
val = readl(port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
val = readl(port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
val = readl(port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
mode = readl(port->membase + AML_UART_CONTROL);
writel(mode, port->membase + AML_UART_CONTROL);
writel(mode, port->membase + AML_UART_CONTROL);
if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
val = readl(port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
val = readl(port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
val = readl(port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
val = readl(port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);
val = readl(port->membase + AML_UART_CONTROL);
writel(tmp, port->membase + AML_UART_CONTROL);
writel(val, port->membase + AML_UART_CONTROL);