HDP_MEM_COHERENCY_FLUSH_CNTL
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));