HDMI_READ
HDMI_READ(HDMI_HCR);
HDMI_READ(0x51a8);
HDMI_READ(HDMI_AUDIO_CTRL);
HDMI_READ(0x51a8);
HDMI_READ(HDMI_AUDIO_CTRL);
HDMI_READ(HDMI_HCR);
temp = HDMI_READ(HDMI_HSR);
HDMI_READ(HDMI_HI2CHCR);
temp = HDMI_READ(HDMI_HI2CRDB0 + (i * 4));
temp = HDMI_READ(HDMI_HISR);
HDMI_READ(HDMI_HISR);
temp = HDMI_READ(HDMI_HI2CHCR);
HDMI_READ(HDMI_HI2CHCR);
temp = HDMI_READ(HDMI_HISR);
HDMI_READ(HDMI_HISR);
temp = HDMI_READ(HDMI_HI2CHCR);
HDMI_READ(HDMI_HI2CHCR);
stat = HDMI_READ(HDMI_HISR);
HDMI_READ(HDMI_HISR);
temp = HDMI_READ(HDMI_HICR);
HDMI_READ(HDMI_HICR);
HDMI_READ(HDMI_HICR);
reg = HDMI_READ(HDMI_MISC_CONTROL);
reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
reg = HDMI_READ(HDMI_GCP_WORD_1);
reg = HDMI_READ(HDMI_GCP_CONFIG);
reg = HDMI_READ(HDMI_MISC_CONTROL);
drift = HDMI_READ(HDMI_FIFO_CTL);
ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
HDMI_READ(HDMI_SCHEDULER_CONTROL) |
(HDMI_READ(HDMI_VID_CTL) &
HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
HDMI_READ(HDMI_SCHEDULER_CONTROL) |
ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
HDMI_READ(HDMI_SCHEDULER_CONTROL) &
ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
hotplug = HDMI_READ(HDMI_HOTPLUG);
HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
value = HDMI_READ(HDMI_CEC_CNTRL_1);
cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
val = HDMI_READ(HDMI_CEC_CNTRL_5);
HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
(HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
val = HDMI_READ(HDMI_CEC_CNTRL_1);
value = HDMI_READ(HDMI_CEC_CNTRL_1);
HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
HDMI_READ(HDMI_VID_CTL) &
HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
HDMI_READ(HDMI_TX_PHY_PLL_RESET_CTL) &
HDMI_READ(HDMI_TX_PHY_PLL_RESET_CTL) |
HDMI_READ(HDMI_TX_PHY_CTL_0) &
HDMI_READ(HDMI_TX_PHY_CTL_0) |
HDMI_READ(HDMI_TX_PHY_RESET_CTL) &
HDMI_READ(HDMI_RM_CONTROL) |
(HDMI_READ(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1) &
(HDMI_READ(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2) &
HDMI_READ(HDMI_TX_PHY_PLL_CTL_1) |
HDMI_READ(HDMI_RM_FORMAT) |
HDMI_READ(HDMI_TX_PHY_PLL_CFG) |
HDMI_READ(HDMI_TX_PHY_CTL_1) |
HDMI_READ(HDMI_TX_PHY_RESET_CTL) &
HDMI_READ(HDMI_TX_PHY_RESET_CTL) |
HDMI_READ(HDMI_TX_PHY_POWERDOWN_CTL) &
HDMI_READ(HDMI_TX_PHY_POWERDOWN_CTL) |