drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

113

mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

114

mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

116

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

117

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

119

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

120

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

122

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

123

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

124

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

142

tmp = readl(hdmi_phy->regs + HDMI_CON6);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

182

mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

183

mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

186

mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

208

mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

211

mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

212

mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

56

mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

57

mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

60

mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

84

mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

87

mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

88

mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

197

mtk_phy_update_bits(base + HDMI_CON6,