HDMI_CEC_DBG_3
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);