HDMI_ACR_44_0
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
uint32_t HDMI_ACR_44_0;
SRI(HDMI_ACR_44_0, DIG, id),\
REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
uint32_t HDMI_ACR_44_0;
SRI(HDMI_ACR_44_0, DIG, id),\
REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
SRI(HDMI_ACR_44_0, DIG, id),\
SRI(HDMI_ACR_44_0, DIG, id),\
SRI(HDMI_ACR_44_0, DIG, id),\
SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
SRI_ARR(HDMI_ACR_44_0, DIG, id),\
SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));