HDMI_ACR_32_1
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
uint32_t HDMI_ACR_32_1;
SRI(HDMI_ACR_32_1, DIG, id),\
REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
uint32_t HDMI_ACR_32_1;
SRI(HDMI_ACR_32_1, DIG, id),\
REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
SRI(HDMI_ACR_32_1, DIG, id),\
SRI(HDMI_ACR_32_1, DIG, id),\
SRI(HDMI_ACR_32_1, DIG, id),\
SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
SRI_ARR(HDMI_ACR_32_1, DIG, id),\
SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);