HCLK_VPU
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0,
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0,
GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
#define CLK_NR_CLKS (HCLK_VPU + 1)
#define CLK_NR_CLKS (HCLK_VPU + 1)