HCLK_SDIO1
D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0),
GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0,