HCLK
hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre",
LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
ALIAS(HCLK, NULL, "hclk"),
mmc->f_min = HCLK / 512;
mmc->f_max = HCLK;
while (ios->clock < HCLK / div)
par->HCLK = (1000000000 + (lineclock / 2)) / lineclock;
u32 HCLK; /* Hor Clock */