HCLGE_MISC_VECTOR_REG_BASE
{HCLGE_MISC_VECTOR_REG_BASE, "vector0 interrupt enable status"},
vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,