HAL_SEQ_WCSS_UMAC_WBM_REG
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;
HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR,
HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_SIZE_ADDR,
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_SEQ_WCSS_UMAC_WBM_REG +
u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG;
HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(hal);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(hal);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_PPE_RELEASE_RING_HP;
HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(hal);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(hal);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;