arch/arm/mach-clps711x/board-dt.c

42

DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

385

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

387

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

960

tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

967

tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

622

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

624

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1057

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1420

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1014

temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1730

if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT))

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

652

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1604

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

672

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

816

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1516

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

519

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

663

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

468

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

601

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

459

mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

594

temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

441

mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_SDMA_MCU_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

576

temp = REG_SET_FIELD(temp, SDMA0_SDMA_MCU_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

103

if (!REG_GET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT)) {

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

173

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

84

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

96

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

163

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

80

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0);