drivers/crypto/caam/caamalg_qi2.c

3046

#define MAX_CTX_LEN (HASH_MSG_LEN + SHA512_DIGEST_SIZE)

drivers/crypto/caam/caamalg_qi2.c

4566

static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,

drivers/crypto/caam/caamalg_qi2.c

4567

HASH_MSG_LEN + SHA1_DIGEST_SIZE,

drivers/crypto/caam/caamalg_qi2.c

4568

HASH_MSG_LEN + 32,

drivers/crypto/caam/caamalg_qi2.c

4569

HASH_MSG_LEN + SHA256_DIGEST_SIZE,

drivers/crypto/caam/caamalg_qi2.c

4570

HASH_MSG_LEN + 64,

drivers/crypto/caam/caamalg_qi2.c

4571

HASH_MSG_LEN + SHA512_DIGEST_SIZE };

drivers/crypto/caam/caamhash.c

1774

static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,

drivers/crypto/caam/caamhash.c

1775

HASH_MSG_LEN + SHA1_DIGEST_SIZE,

drivers/crypto/caam/caamhash.c

1776

HASH_MSG_LEN + 32,

drivers/crypto/caam/caamhash.c

1777

HASH_MSG_LEN + SHA256_DIGEST_SIZE,

drivers/crypto/caam/caamhash.c

1778

HASH_MSG_LEN + 64,

drivers/crypto/caam/caamhash.c

1779

HASH_MSG_LEN + SHA512_DIGEST_SIZE };

drivers/crypto/caam/caamhash.c

90

#define MAX_CTX_LEN (HASH_MSG_LEN + SHA512_DIGEST_SIZE)