HAL_SEQ_WCSS_UMAC_CE0_DST_REG
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB +
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP +
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) +
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP +
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_RING_HP;
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal);
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal);
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) +
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_STATUS_RING_HP;
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal);
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal);
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_RING_HP;
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal);
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal);
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) +
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_STATUS_RING_HP;
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal);
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal);