drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

728

int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

734

AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

759

if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

762

int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

771

uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

857

AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

864

bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

889

AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

948

if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

951

micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

1134

AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

352

max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

353

num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

354

data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

356

AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1885

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1975

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1978

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1979

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1980

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1981

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1982

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1995

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2002

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2005

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2006

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2007

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2008

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2009

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2017

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2021

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1832

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1914

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1917

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1918

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1919

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1920

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1921

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1930

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12492

linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12494

linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12496

linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12497

AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

12498

AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

185

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

188

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

189

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

190

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

191

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

192

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

205

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

211

AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);