drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

189

[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

207

#define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS)

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

236

for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i)

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

737

for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

1070

for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) {

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

1614

for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) {

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

352

u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

392

u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

393

u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

422

struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

428

u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

429

u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

432

u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

433

u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

451

struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

drivers/gpu/drm/xe/abi/guc_klvs_abi.h

244

(GUC_KLV_VGT_POLICY_ENGINE_GROUP_MAX_COUNT * GUC_MAX_ENGINE_CLASSES)

drivers/gpu/drm/xe/abi/guc_scheduler_abi.h

54

u32 engines[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c

569

groups, num_groups * GUC_MAX_ENGINE_CLASSES);

drivers/gpu/drm/xe/xe_guc_ads.c

535

for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i)

drivers/gpu/drm/xe/xe_guc_capture.c

303

#define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * GUC_MAX_INSTANCES_PER_CLASS)

drivers/gpu/drm/xe/xe_guc_engine_activity.c

310

for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)

drivers/gpu/drm/xe/xe_guc_engine_activity_types.h

56

struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

drivers/gpu/drm/xe/xe_guc_fwif.h

124

u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

drivers/gpu/drm/xe/xe_guc_fwif.h

125

u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/xe/xe_guc_fwif.h

131

struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

drivers/gpu/drm/xe/xe_guc_fwif.h

137

u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/xe/xe_guc_fwif.h

138

u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/xe/xe_guc_fwif.h

141

u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/xe/xe_guc_fwif.h

142

u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];

drivers/gpu/drm/xe/xe_guc_fwif.h

160

struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

drivers/gpu/drm/xe/xe_guc_fwif.h

172

struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];

drivers/gpu/drm/xe/xe_guc_fwif.h

95

u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];