arch/mips/kvm/entry.c

166

UASM_i_ADDIU(&p, GPR_K1, GPR_SP, -(int)sizeof(struct pt_regs));

arch/mips/kvm/entry.c

170

UASM_i_SW(&p, i, offsetof(struct pt_regs, regs[i]), GPR_K1);

arch/mips/kvm/entry.c

175

UASM_i_SW(&p, GPR_V0, offsetof(struct pt_regs, cp0_status), GPR_K1);

arch/mips/kvm/entry.c

178

kvm_mips_build_save_scratch(&p, GPR_V1, GPR_K1);

arch/mips/kvm/entry.c

184

UASM_i_ADDIU(&p, GPR_K1, GPR_A0, offsetof(struct kvm_vcpu, arch));

arch/mips/kvm/entry.c

190

UASM_i_SW(&p, GPR_SP, offsetof(struct kvm_vcpu_arch, host_stack), GPR_K1);

arch/mips/kvm/entry.c

193

UASM_i_SW(&p, GPR_GP, offsetof(struct kvm_vcpu_arch, host_gp), GPR_K1);

arch/mips/kvm/entry.c

204

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, guest_ebase), GPR_K1);

arch/mips/kvm/entry.c

246

UASM_i_LW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, pc), GPR_K1);

arch/mips/kvm/entry.c

254

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, host_pgd), GPR_K1);

arch/mips/kvm/entry.c

265

(int)offsetof(struct kvm_vcpu, arch), GPR_K1);

arch/mips/kvm/entry.c

305

GPR_K1);

arch/mips/kvm/entry.c

345

if (i == GPR_K0 || i == GPR_K1)

arch/mips/kvm/entry.c

347

UASM_i_LW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), GPR_K1);

arch/mips/kvm/entry.c

352

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, hi), GPR_K1);

arch/mips/kvm/entry.c

355

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, lo), GPR_K1);

arch/mips/kvm/entry.c

360

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, gprs[GPR_K0]), GPR_K1);

arch/mips/kvm/entry.c

361

UASM_i_LW(&p, GPR_K1, offsetof(struct kvm_vcpu_arch, gprs[GPR_K1]), GPR_K1);

arch/mips/kvm/entry.c

394

UASM_i_MTC0(&p, GPR_K1, scratch_tmp[0], scratch_tmp[1]);

arch/mips/kvm/entry.c

397

UASM_i_MFC0(&p, GPR_K1, scratch_vcpu[0], scratch_vcpu[1]);

arch/mips/kvm/entry.c

400

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu, arch.gprs[GPR_K0]), GPR_K1);

arch/mips/kvm/entry.c

409

UASM_i_MFC0(&p, GPR_K1, C0_PGD);

arch/mips/kvm/entry.c

410

uasm_i_lddir(&p, GPR_K0, GPR_K1, 3); /* global page dir */

arch/mips/kvm/entry.c

412

uasm_i_lddir(&p, GPR_K1, GPR_K0, 1); /* middle page dir */

arch/mips/kvm/entry.c

414

uasm_i_ldpte(&p, GPR_K1, 0); /* even */

arch/mips/kvm/entry.c

415

uasm_i_ldpte(&p, GPR_K1, 1); /* odd */

arch/mips/kvm/entry.c

430

build_get_pmde64(&p, &l, &r, GPR_K0, GPR_K1); /* get pmd in GPR_K1 */

arch/mips/kvm/entry.c

432

build_get_pgde32(&p, GPR_K0, GPR_K1); /* get pgd in GPR_K1 */

arch/mips/kvm/entry.c

437

build_get_ptep(&p, GPR_K0, GPR_K1);

arch/mips/kvm/entry.c

438

build_update_entries(&p, GPR_K0, GPR_K1);

arch/mips/kvm/entry.c

445

UASM_i_MFC0(&p, GPR_K1, scratch_vcpu[0], scratch_vcpu[1]);

arch/mips/kvm/entry.c

448

UASM_i_LW(&p, GPR_K0, offsetof(struct kvm_vcpu, arch.gprs[GPR_K0]), GPR_K1);

arch/mips/kvm/entry.c

450

UASM_i_MFC0(&p, GPR_K1, scratch_tmp[0], scratch_tmp[1]);

arch/mips/kvm/entry.c

480

UASM_i_MTC0(&p, GPR_K1, scratch_tmp[0], scratch_tmp[1]);

arch/mips/kvm/entry.c

483

UASM_i_MFC0(&p, GPR_K1, scratch_vcpu[0], scratch_vcpu[1]);

arch/mips/kvm/entry.c

484

UASM_i_ADDIU(&p, GPR_K1, GPR_K1, offsetof(struct kvm_vcpu, arch));

arch/mips/kvm/entry.c

487

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, gprs[GPR_K0]), GPR_K1);

arch/mips/kvm/entry.c

535

if (i == GPR_K0 || i == GPR_K1)

arch/mips/kvm/entry.c

537

UASM_i_SW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), GPR_K1);

arch/mips/kvm/entry.c

543

UASM_i_SW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, hi), GPR_K1);

arch/mips/kvm/entry.c

546

UASM_i_SW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, lo), GPR_K1);

arch/mips/kvm/entry.c

552

UASM_i_SW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, gprs[GPR_K1]), GPR_K1);

arch/mips/kvm/entry.c

564

UASM_i_SW(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, pc), GPR_K1);

arch/mips/kvm/entry.c

568

GPR_K1);

arch/mips/kvm/entry.c

571

uasm_i_sw(&p, GPR_K0, offsetof(struct kvm_vcpu_arch, host_cp0_cause), GPR_K1);

arch/mips/kvm/entry.c

576

host_cp0_badinstr), GPR_K1);

arch/mips/kvm/entry.c

582

host_cp0_badinstrp), GPR_K1);

arch/mips/kvm/entry.c

612

GPR_K1);

arch/mips/kvm/entry.c

628

GPR_K1);

arch/mips/kvm/entry.c

636

GPR_K1);

arch/mips/kvm/entry.c

647

offsetof(struct kvm_vcpu_arch, host_pgd), GPR_K1);

arch/mips/kvm/entry.c

663

offsetof(struct kvm_vcpu_arch, host_cp0_guestctl0), GPR_K1);

arch/mips/kvm/entry.c

689

UASM_i_LW(&p, GPR_GP, offsetof(struct kvm_vcpu_arch, host_gp), GPR_K1);

arch/mips/kvm/entry.c

692

UASM_i_LW(&p, GPR_SP, offsetof(struct kvm_vcpu_arch, host_stack), GPR_K1);

arch/mips/kvm/entry.c

758

uasm_i_move(&p, GPR_K1, GPR_S0);

arch/mips/kvm/entry.c

759

UASM_i_ADDIU(&p, GPR_K1, GPR_K1, offsetof(struct kvm_vcpu, arch));

arch/mips/kvm/entry.c

796

UASM_i_LW(&p, GPR_T0, offsetof(struct kvm_vcpu_arch, guest_ebase), GPR_K1);

arch/mips/kvm/entry.c

834

UASM_i_LW(&p, GPR_K1, offsetof(struct kvm_vcpu_arch, host_stack), GPR_K1);

arch/mips/kvm/entry.c

835

UASM_i_ADDIU(&p, GPR_K1, GPR_K1, -(int)sizeof(struct pt_regs));

arch/mips/kvm/entry.c

848

UASM_i_LW(&p, i, offsetof(struct pt_regs, regs[i]), GPR_K1);

arch/mips/kvm/entry.c

857

UASM_i_LW(&p, GPR_RA, offsetof(struct pt_regs, regs[GPR_RA]), GPR_K1);

arch/mips/mm/tlbex.c

1260

htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, GPR_K0, GPR_K1,

arch/mips/mm/tlbex.c

1275

uasm_i_dmfc0(&p, GPR_K1, C0_ENTRYHI);

arch/mips/mm/tlbex.c

1276

uasm_i_xor(&p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1277

uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, 62);

arch/mips/mm/tlbex.c

1280

uasm_i_or(&p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1286

build_get_pmde64(&p, &l, &r, GPR_K0, GPR_K1); /* get pmd in GPR_K1 */

arch/mips/mm/tlbex.c

1288

build_get_pgde32(&p, GPR_K0, GPR_K1); /* get pgd in GPR_K1 */

arch/mips/mm/tlbex.c

1292

build_is_huge_pte(&p, &r, GPR_K0, GPR_K1, label_tlb_huge_update);

arch/mips/mm/tlbex.c

1295

build_get_ptep(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1296

build_update_entries(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1304

UASM_i_LW(&p, htlb_info.huge_pte, 0, GPR_K1);

arch/mips/mm/tlbex.c

1305

build_huge_update_entries(&p, htlb_info.huge_pte, GPR_K1);

arch/mips/mm/tlbex.c

1311

build_get_pgd_vmalloc64(&p, &l, &r, GPR_K0, GPR_K1, vmalloc_mode);

arch/mips/mm/tlbex.c

1485

uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0,

arch/mips/mm/tlbex.c

1487

uasm_il_beqz(&p, &r, GPR_K1, label_vmalloc);

arch/mips/mm/tlbex.c

1495

uasm_i_dmfc0(&p, GPR_K1, C0_PGD);

arch/mips/mm/tlbex.c

1497

uasm_i_lddir(&p, GPR_K0, GPR_K1, 3); /* global page dir */

arch/mips/mm/tlbex.c

1499

uasm_i_lddir(&p, GPR_K1, GPR_K0, 1); /* middle page dir */

arch/mips/mm/tlbex.c

1501

uasm_i_ldpte(&p, GPR_K1, 0); /* even */

arch/mips/mm/tlbex.c

1502

uasm_i_ldpte(&p, GPR_K1, 1); /* odd */

arch/mips/mm/tlbex.c

1521

UASM_i_LA(&p, GPR_K1, (unsigned long)tlb_do_page_fault_0);

arch/mips/mm/tlbex.c

1522

uasm_i_jr(&p, GPR_K1);

arch/mips/mm/tlbex.c

1888

build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1889

build_pte_present(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbl);

arch/mips/mm/tlbex.c

1891

build_make_valid(&p, &r, GPR_K0, GPR_K1, -1);

arch/mips/mm/tlbex.c

1892

build_r3000_tlb_reload_write(&p, &l, &r, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1918

build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1919

build_pte_writable(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbs);

arch/mips/mm/tlbex.c

1921

build_make_write(&p, &r, GPR_K0, GPR_K1, -1);

arch/mips/mm/tlbex.c

1922

build_r3000_tlb_reload_write(&p, &l, &r, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1948

build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

1949

build_pte_modifiable(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbm);

arch/mips/mm/tlbex.c

1951

build_make_write(&p, &r, GPR_K0, GPR_K1, -1);

arch/mips/mm/tlbex.c

1952

build_r3000_pte_reload_tlbwi(&p, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

2069

uasm_i_dmfc0(&p, GPR_K1, C0_ENTRYHI);

arch/mips/mm/tlbex.c

2070

uasm_i_xor(&p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

2071

uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, 62);

arch/mips/mm/tlbex.c

2074

uasm_i_or(&p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

341

r.r2 = GPR_K1;

arch/mips/mm/tlbex.c

354

UASM_i_LA(p, GPR_K1, (long)&handler_reg_save);

arch/mips/mm/tlbex.c

355

UASM_i_ADDU(p, GPR_K0, GPR_K0, GPR_K1);

arch/mips/mm/tlbex.c

363

r.r1 = GPR_K1;

arch/mips/mm/tlbex.c

398

uasm_i_lui(&p, GPR_K1, uasm_rel_hi(pgdc)); /* cp0 delay */

arch/mips/mm/tlbex.c

399

uasm_i_lw(&p, GPR_K1, uasm_rel_lo(pgdc), GPR_K1);

arch/mips/mm/tlbex.c

402

uasm_i_addu(&p, GPR_K1, GPR_K1, GPR_K0);

arch/mips/mm/tlbex.c

404

uasm_i_lw(&p, GPR_K1, 0, GPR_K1); /* cp0 delay */

arch/mips/mm/tlbex.c

406

uasm_i_addu(&p, GPR_K1, GPR_K1, GPR_K0);

arch/mips/mm/tlbex.c

407

uasm_i_lw(&p, GPR_K0, 0, GPR_K1);

arch/mips/mm/tlbex.c

410

uasm_i_mfc0(&p, GPR_K1, C0_EPC); /* cp0 delay */

arch/mips/mm/tlbex.c

412

uasm_i_jr(&p, GPR_K1);