drivers/gpu/drm/radeon/cik.c

7297

rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7299

rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7302

rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7304

rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7308

rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7310

rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7315

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,

drivers/gpu/drm/radeon/cik.c

7318

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,

drivers/gpu/drm/radeon/cik.c

7331

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,

drivers/gpu/drm/radeon/cik.c

7334

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,

drivers/gpu/drm/radeon/cik.c

7348

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,

drivers/gpu/drm/radeon/cik.c

7351

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,

drivers/gpu/drm/radeon/evergreen.c

4629

grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

4636

WREG32(GRPH_INT_STATUS + crtc_offsets[j],

drivers/gpu/drm/radeon/si.c

6137

grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);

drivers/gpu/drm/radeon/si.c

6144

WREG32(GRPH_INT_STATUS + crtc_offsets[j],