Symbol: GRPH_INT_CONTROL
drivers/gpu/drm/radeon/cik.c
6893
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
drivers/gpu/drm/radeon/cik.c
6894
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
drivers/gpu/drm/radeon/cik.c
6897
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
drivers/gpu/drm/radeon/cik.c
6898
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
drivers/gpu/drm/radeon/cik.c
6901
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
drivers/gpu/drm/radeon/cik.c
6902
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
drivers/gpu/drm/radeon/cik.c
7245
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
drivers/gpu/drm/radeon/cik.c
7247
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
drivers/gpu/drm/radeon/cik.c
7251
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
drivers/gpu/drm/radeon/cik.c
7253
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
drivers/gpu/drm/radeon/cik.c
7257
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
drivers/gpu/drm/radeon/cik.c
7259
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
drivers/gpu/drm/radeon/evergreen.c
4484
WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
drivers/gpu/drm/radeon/evergreen.c
4590
WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
drivers/gpu/drm/radeon/si.c
5947
WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
drivers/gpu/drm/radeon/si.c
6105
WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);